A series/parallel/series shift register memory comprises a substrate on which there are provided storage positions for multivalent data elements. There is provided a redundancy generator for generating one or more redundant code elements on the basis of a group of data elements, said redundant code elements being applied to the series input of the shift register memory later than the associated data elements. The code elements are conducted through parallel-connected storage registers which are shorter than those used for the associated data elements, so that a redundancy reducer receives the redundant code elements from a series output before the associated data elements appear on this series output. The reduction of the storage registers, expressed in periods of the shift drive, can be performed in different ways from a technological point of view.
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