Method and arrangement for increasing the performance capability of data-processing installations having data which have errors and are stored in buffer stores, especially in cache stores

摘要

Individual control bits (W) to identify a change are allocated to the smallest possible subunits, for example bytes, of a data block. These control bits are linked together with the error signals (PERR...) which are derived from the associated parity characters of the subunits, unchanged subunits in which there are errors being prevented from being accepted by the working memory (ASP). In order that data units (DW...) of blocks which have no errors can always be transmitted in the framework of a block cycle having a single control command, every relocation starts with a block cycle. If an error is identified at the same time, acceptance is stopped by a blocking signal (W.INH) until the end of the block cycle, or the block cycle is terminated. Subsequently, all the data units (DW...), or only the data units which have not yet been transmitted and are affected by a change, are transmitted using an individual command control, subunits which are to be prevented from being accepted being marked by individual accompanying signals (BYTE.SEL..=0). Relocation is also possible in a block cycle if the individual accompanying signals (BYTE.SEL...) are effective from the start and the blocking signal (W.INH) is inhibited. Relocation of erroneously changed subunits as well, by a separate signal (SPERR), which on the one hand modifies the accompanying signals which inhibit acceptance and on the other hand forces acceptance by the working memory (ASP), without a storage error message ... Original abstract incomplete. IMAGE