Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction

摘要

Each of a plurality of stored pointers identifies and accesses one of a plurality of hardware registers in a central processing unit (CPU). Each pointer is associated with and corresponds to one of a limited number of general purpose registers addressable by various fields in a program instruction of the data processing system. At least one program instruction calls for transfer of data from a particular main storage location to a general purpose register (GPR) identified by a field in the program instruction. The GPR identified as the destination for the data is renamed by assigning a pointer value to provide access to one of the plurality of associated hardware registers. A subsequent load instruction involving the same particular main storage location determines if the data from the previous load instruction is still stored in one of the hardware registers and determines the associated pointer value. The data in the hardware register is made immediately available to the CPU before completion of the access to main storage. The pointer value is associated with, and made to correspond to the destination GPR of the subsequent load instruction. Other instructions which require access to instruction addressable GPR's cause access to the corresponding pointer value to provide access to the corresponding hardware register for purposes of data processing.