The error detection correction device and its manner null of IC chitsupu which accompanies the automatic self diagnostic of chitsupu

摘要

Error detecting and correction operations for a plurality of input bits comprised of input data bits (ID0-ID39) and associated check bits (CB0-CB7) are implemented using two IC chips in order to overcome chip output limitations. In addition, redundancies derived from the use of two IC chips are employed to provide automatic self-checking of the detecting operation of each chip. The use of two identical IC chips (10 and 10') for this purpose is made possible by employing a specifically chosen inversely symmetrical Hamming code and by wiring the input data bits and the input check bits in an inverse manner with respect to the input terminals of the two IC chips. As a result, even though each IC chip performs the same error detecting and correcting operations, it does so inversely with respect to the input data bits and the input check bits so that each IC chip is able to provide one-half of the required output bits.