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PREFERENCE LOGIC UNIT FOR DETERMINING PREFERENCE ORDER OF ACCESSING MEMORY IN DATA PROCESSOR
PREFERENCE LOGIC UNIT FOR DETERMINING PREFERENCE ORDER OF ACCESSING MEMORY IN DATA PROCESSOR
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机译:确定数据处理器中访问内存优先顺序的优先逻辑单元
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摘要
An improved priority logic scheme for setting priority values determining priority of interrupts. Multi-level priority allows for varied priority values for single word and multiple-word block segment transfers. Registers allow for programmable priority values which can modify priority values during operation. Simplicity of the invention provides for priority circuitry which does not depend on clock cycles. Flexiblity of the circuitry allows for additional devices to be implemented within the scheme. The invention is described as developed in a single semiconductor chip with other processors to provide a single graphics chip capability.
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