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MEMORY SYSTEM ABLE TO REARRANGE DEFECTS DURING OPERATION

机译:能够在操作期间重新发现缺陷的内存系统

摘要

A method is disclosed for operating a fault tolerant memory system which is provided with a fault alignment exclusion mechanism of the type disclosed in copending application Ser. No. 388,834. The method allows the assignment of a new permute vector to the fault alignment mechanism even though the memory is operating and storing user data. The method rearranges the data in the affected column by transferring data in one chip to another chip in the column through a buffer under the control of the old and new permute vectors. The transfer operation involves transferring the data at the same bit position from each chip in the column to a buffer under the control of the old permute vector and then transferring the data from the buffer to the same bit positions in other chips in the column determined by the new permute vector. The memory is then returned to the user for normal operation.
机译:公开了一种用于操作容错存储系统的方法,该系统具有在共同待决的申请Ser中公开的类型的故障对准排除机制。第388,834号。即使存储器正在运行并存储用户数据,该方法也可以将新的置换向量分配给故障对齐机制。该方法通过在旧的和新的置换向量的控制下通过缓冲器将一个芯片中的数据传输到该列中的另一芯片,来重新排列受影响列中的数据。传输操作包括在旧置换向量的控制下,将列中每个芯片的相同位位置处的数据传输到缓冲区,然后将数据传输至列中其他芯片中相同位位置的缓冲区,由新的置换向量。然后将内存返回给用户以进行正常操作。

著录项

  • 公开/公告号JPS6237423B2

    专利类型

  • 公开/公告日1987-08-12

    原文格式PDF

  • 申请/专利权人 INTAANASHONARU BIJINESU MASHIINZU CORP;

    申请/专利号JP19830102951

  • 发明设计人 FUIRITSUPU MIIDO RAIAN;

    申请日1983-06-10

  • 分类号G06F12/16;G11C29/00;

  • 国家 JP

  • 入库时间 2022-08-22 07:23:27

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