PURPOSE:To decrease the delay time by multiplexing all 2nd order group trans mission bits and arranging synchronizing frame bits scatteringly at every frame length/N so as to decrease the memory capacity for phase matching. CONSTITUTION:Frame synchronizing is bits F1-F4 consisting of u-bit respective ly are arranged scatteringly to divide one frame length, i.e., a time T0, into 4 equally. The 2nd order group signals D1-D4 subjected to time division multi plex are formed to have the arrangement of multiplex unit V, that is, n-time repetition of up to m-set 2nd order group signal input number subjected to sequential multiplex in the information unit of 8-bit normally. When the 2nd order group signal P has, e.g., 789-bit, q=11-bit is added as an excess bit and time division multiplex is applied by a multiplexer 1 from the signal 10 of 800-bit number to generate the 3rd or 4th order group signal 11. In adopting the frame constitution as above and inputting the signal to a line edit equipment 24, the signals 12, 13 require the delay by T1, Tn to a reference frame 27, but are enough for the delay of T0/4 only at most to the time t0 and the memory capacity is saved.
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