The high potential hold circuit comprises a high potential node and a high potential hold enhancement mode MOS transistor to hold a potential of the high potential node by setting the high potential hold transistor in an non-conducting state after the node is charged, having one end connected to a first input signal and the other end connected to the high potential node. A discharge enhancement mode MOS transistor discharges the potential of the high potential node, having one end connected to the other end of the ground potential connected to the high potential node and a gate connected to a second input signal.
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