DATA PROCESSING SYSTEM WITH GUEST ARCHITECTURAL SUPPORT

摘要

A data processing system includes TLB hardware (DLAT 131) in a CP that receives the results of double-level address translations to eliminate the need for having shadow tables for the second-level in a virtual machine (VM) environment. Each TLB entry contains hardware (G-Field) which indicates whether the address sent by the CP Instruction Execution (IE) unit for translation is a guest or host/native request, and for a guest request if it is a real or virtual address (R-Field). Intermediate translations for a double-level translation are inhibited from being loaded into the TLB (line 54A). Guest entries are purged from the TLB without disturbing any host entries (DLAT purge control 140). An accelerated preferred guest mode in the CP forces its hardware adder translation hardware (113, 117) to translate each accelerated preferred guest request, since it requires only a single level translation. A non-accelerated guest request is instead translated by microcode in the IE. A limit check register (102) is provided to check preferred guest addresses without causing performance degradation.