Circuit arrangement to evaluate the vertical synchronisation information from the synchronisation signal part of an FBAS (colour video) or BAS (video) signal of various television standards

摘要

To evaluate the vertical synchronisation information from the synchronisation signal part of FBAS or BAS signals with varying line duration and/or picture frequency and/or equalising pulse configuration, by detecting the time area of the pre-equalising, main equalising and post-equalising pulses contained in the synchronisation signal part, a signal which characterises the approximate time position of the vertical synchronisation information is generated and fed to a gate circuit. The gate circuit is formed so that, during the first state of the output signal of a detector circuit, it transmits the supplied synchronisation signal part to the clock input of a shift register, and, during the second state of the output signal of the detector circuit, it blocks it. The special binary information at the parallel data inputs of the shift register is selected so that, when the loaded special information is read according to the gated synchronisation signal part which is fed to the clock input, a vertical synchronisation pulse is synthesised at the shift register output.