首页> 外国专利> CONTROL SYSTEM FOR EXECUTION OF SIGNAL PROCESSOR INSTRUCTION IN MULTIPROCESSOR SYSTEM

CONTROL SYSTEM FOR EXECUTION OF SIGNAL PROCESSOR INSTRUCTION IN MULTIPROCESSOR SYSTEM

机译:在多处理器系统中执行信号处理器指令的控制系统

摘要

PURPOSE:To perform secure control over competition in the execution of signal processor instructions and to improve the processing efficiency of a system by providing a signal processor instruction control bit in the control register of every system. CONSTITUTION:Control bits 2 and 5 in control registers 1 and 4 represents a signal processor instruction control bit SIGP BUSY. When the high priority computer of a system 0 sends an instruction SIGP to the low priority computer of a system 1, its microprogram mu1 is started. When the computer of the system 1 sends the instruction SIGP to the computer of the system 0, the bit SIGP BUSY of the high priority computer of the other system is checked firstly. When the bit is off, it is judged that there is no competition, and the instruction SIGP of its system is presumed as effective and executed. Thus, the control bit is provided in the control register of each system to perform the secure control over competition, improving the processing efficiency of the system.
机译:目的:通过在每个系统的控制寄存器中提供信号处理器指令控制位,来对信号处理器指令执行中的竞争进行安全控制,并提高系统的处理效率。组成:控制寄存器1和4中的控制位2和5代表信号处理器指令控制位SIGP BUSY。当系统0的高优先级计算机向系统1的低优先级计算机发送指令SIGP时,其微程序mu1将启动。当系统1的计算机向系统0的计算机发送指令SIGP时,首先检查另一个系统的高优先级计算机的SIGP BUSY位。当该位为OFF时,判断为没有竞争,并且假定其系统的指令SIGP有效并执行。因此,在每个系统的控制寄存器中提供控制位以执行对竞争的安全控制,从而提高了系统的处理效率。

著录项

  • 公开/公告号JPS6310464B2

    专利类型

  • 公开/公告日1988-03-07

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19820228856

  • 发明设计人 HARA KAZUHIRO;

    申请日1982-12-23

  • 分类号G06F12/00;G06F9/52;G06F15/16;G06F15/17;G06F15/177;

  • 国家 JP

  • 入库时间 2022-08-22 07:07:48

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