PURPOSE:To simplify the circuit constitution and to make the bit delay the same by operating/stopping the 2 final stages of shift registers of 8 and 7 stages constituting a 8 consecutive zero detection circuit and a bipolar violation code generating circuit depending on H/L of a selection signal. CONSTITUTION:The 8 shift registers in the consecutive zero detection circuit 1 detect 8 consecutive zeros in an input data, and a code violation code generating circuit 2 gives its detected output to the 7 stage of shift registers, from the output of each stage of which a prescribed bipolar violation rule code is generated. A BNZS code output circuit 3 receives the output of the circuit 2, the output of the circuit 1 and a reference voltage V to output a B8ZS code and a B6ZS code. Since the operation of the final 2-stage of the violation rule code generating circuit 2 and the final stage of the shift register of the consecutive zero detection circuit 1 is stopped by the switching of the code H/L of the selection signal, the state of replacing the 8 consecutive zero into the B8ZS code into the state converting 6 consecutive zero into B6ZS code is switched automatically.
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