PROCESS AND ARRANGEMENT FOR THE DERIVATION OF AN AUXILIARY DATA CADENCE FROM THE CADENCE AND / OR CADENCE PHASE OF A SYNCHRONOUS OR PLESIOCHRONOUS DIGITAL SIGNAL

摘要

A method and apparatus for recovering the clock and/or the clock phase of a synchronous or plesiochronic digital signal provide that logic circuits in gate arrays or cell arrays recover the clock. In an auxiliary clock generator, an auxiliary clock is generated, or auxiliary clocks of the same frequency and different phase relationship extracted therefrom are generated which, conducted by way of a phase correction facility, provide an auxiliary data clock as the recovered clock. In principle, the frequency of the auxiliary clock or auxiliary clocks deviates from that of the auxiliary data clock to be formed. A phase sensor checks whether the active edges of the digital signal and of the auxiliary data clock have approached each other to less than a predetermined time interval and emits a corrections signal as soon as such an event occurs. This signal causes a phase shifting of the auxiliary data clock by switching between the extracted auxiliary clocks and/or by reversing the polarity of the auxiliary clock or of the extracted plurality of auxiliary clocks.