A hardware logic network, operating at real-time data rates, generates a signal which matches the Mth-largest signal of an input data set. To accomplish this signal- matching, the network utilizes an iterative series of value adjustments which cause an intermediate working quantity to converge to a number whose rank in comparison to the input set is the same as that of the true Mth-largest. When test comparisons indicate that the intermediate value's relative rank is too low, the value-adjustment is upward. The adjustment is downward otherwise. Operating upon input data whose range of possible values is limited to a predetermined interval, the system takes as its initial working quantity the midpoint of this interval. The magnitude of the first adjustment is one-half of the remaining interval on either side of the initial approximation. Subsequent magnitude adjustments are in turn one-half of the preceding half-remaining-interval magnitude.;When the number R of inputs is odd and M is set equal to (R+1)12, the network becomes a real-time median filter.
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