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RANDOM ACCESS MEMORY SYSTEM HAVING HIGH-SPEED SERIAL DATA PATHS
RANDOM ACCESS MEMORY SYSTEM HAVING HIGH-SPEED SERIAL DATA PATHS
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机译:具有高速串行数据路径的随机访问存储器系统
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摘要
To substantially increase the bandwidth of a random access memory (RAM), a shift register is disposed within the memory array such that the shift register lies parallel to the word lines and is connected to at least individual ones of the bit lines contained within the array. Separate high-speed serial input and output lines are provided by the shift register. These lines are in addition to and operate independently of the slower speed input and output lines normally provided by the RAM. Through this arrangement, a row of data can be transferred to and from the memory array at a rate substantially faster than the single-bit access rate of the RAM.
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