On-line, limited mode, built-in fault detection/isolation system for state machines and combinational logic

摘要

A mechanism for the testing of digital signal processing circuitry (state machines and combinational logic) is built-in and continuously on- line with the system being tested. The operation of the signal processing architecture is monitored dynamically, namely across state transitions, employing a parity prediction operator which predicts the parity that should be produced by combining the contents of selected inputs and outputs of the architecture prior to and subsequent to a signal processing transition. If, due to a single bit failure, the predicted parity is not achieved, the output of an error detector will indicate a state other than that corresponding to the predicted parity and thereby report an error. To ensure accurate operation of the error reporting mechanism, the error signal is modulated by a clock signal the frequency of which is relatively low compared with the system clock that controls state transitions. The detection of interconnect wiring faults (e.g. among state machines) is accomplished by executing an exclusive-OR modulation of the digital signals with a prescribed clock signal the frequency of which is lower than the highest signal level transition rate expected on a communication link upstream of transmission over the link whose continuity is being tested. At the downstream end of the link, immediately adjacent entry into the state machine, the link is coupled to an activity detector. If the activity detector fails to detect change of state activity (i.e. the modulating clock) during a prescribed time window, a fault on the link is declared.