Method and structure for synthesizing 2.sup.C Hz from A 2.sup.A.5. sup.B Hz oscillator

摘要

A method and structure is provided for phase locking an output signal having, for example, a desired frequency of 2.sup.C Hz with a reference signal having a frequency of 2.sup.A.5.sup.B Hz. The phase comparison is performed at a high frequency in order to minimize phase noise and spurious signals.