Programmable logic cell with flexible clocking and flexible feedback

摘要

A logic circuit communicating to and from an input/output port in a variety of input modes and in a variety of output modes. The circuit may be configured to have a dedicated, registered, or latched input; and in the output mode to have a registered, combinatorial or latched output. A register/latch, in conjunction with a programmable input select multiplexer, can function as an input, output or buried register or as a transparent latch. A programmable clock select multiplexer selects between a clock/latch enable signal applied at an external pin or a product term generated internally. Clock polarity control is also provided. Asynchronous reset and preset of the register/latch is provided along with polarity control therefor. Dedicated and programmable feedback paths are provided. An output inverter can selectably be enabled from internal signals or from an external pin. The logic circuit can be deployed in banks, each bank electably receiving the same or a different clock. The register/latch can be preloaded via an internally-generated signal or from the external pins.