APPARATUS FOR DELAYING AT LEAST ONE HIGH TRANSMISSION SPEED BINARY DATA SERIES

摘要

PURPOSE: To attain high speed processing with a simple configuration by sending data having been in advance received by n-sets of clocks after the start of data write. CONSTITUTION: Input data Do,...Dm are written in a 1st FIFO register 25 and a write clock is sent thereto. Then write of input data to a 2nd FIFO register 26 and read of data from the 1st register 25 having received data before are conducted at the same time. Then a 1st phase 38 corresponds to write of data Do (1-64) to the 1st FIFO register 25 after initializing (pulse RAZ1), a 2nd phase 39 corresponds to write of data Do (65-128) to the 2nd FIFO register 26 after initializing (pulse RAZ2) and read of data DoR(1-64) delayed by a delay time τof the 1st FIFO register 25 conducted at the same time as the write. Moreover, a 3rd phase 40 corresponds to write of data Do (129-192) to the 1st FIFO register 25 after initializing (pulse RAZ1) and read of data DoR(65-128) delayed by a time τ of the 2nd FIFO register 26 conducted at the same time as the write. Thus, high speed processing is attained with a simple circuit.