PARALLEL PROCESSING COMPUTER WITH ALTERABLE PREFERENCE OF MEMORY ACCESS

摘要

PURPOSE: To improve the performance in a state wherein a lock step is not attained without substantially spoiling the performance when the lock step is obtained by providing a priority changing means which periodically alternates fixed priority levels. CONSTITUTION: Eight high-speed processors, i.e., computing elements(CE) 10 are connected to two central processing cache boards 12 by a switch 14 positioned on the back surface where the CEs 10 and cache boards are inserted. Then a storage element is interleaved and fixed priority levels are assigned to the processors, but when no lock step is present, the fixed priority levels are rotated periodically among the processors. Cycles between rotations of the priority levels are made long enough not to hinder the lock step from being secured, but preferably not made too long to excessively reduce advantages of common use of delay of rotations of the priority levels. Consequently, there is no large loss of the speed in case of the lock step and the processing speed not in the lock step state can be improved.