LINE FAULT TOLERANT SYNCHRONOUS TIMING REFERENCE GENERATOR FOR STATIC VAR GENERATORS

摘要

ABSTRACT OF THE DISCLOSUREA timing reference generator for producing amulti-phase timing reference signal in synchronism with amulti-phase source voltage signal is disclosed. The timingreference generator uses a N stage array of series connect-ed phase-locked loop (PLL) circuits to preserve theprefault condition of an input source signal by opencircuiting at least the Nth stage prior to the propagationof the fault condition signal through the array. The opencircuited stage acts like a flywheel to preserve theprefault condition of the source signal. This output canbe used to replace the lost source signal until the faultcondition has cleared. The output of the first PLL is usedto provide the timing reference signals. This arrangementallows for sensing delays in establishing the occurrence ofa fault and the consequent delay in activation of theflywheel. The first PLL comprises a positive sequence typephase detector and series connected band reject harmonicfilters in order to eliminate phase errors caused by inputvoltage unbalance and input harmonic content. SubsequentPLL circuits are of the zero phase error type. Multiplefaults are tolerated if two stages of the array are con-nected in parallel and alternately operated as flywheels.The flywheels are sequenced so that one is kept operatingas a flywheel while the other one settles.