CMOS unit cell and method for the automatic layout of such a cell

摘要

A basic cell constructed in accordance with the CMOS technique for building electronic circuits is provided, wherein a plurality of transistors, maximally four transistors, are arranged next to one another. First interconnects essentially composed of polysilicon are arranged parallel to the extent of the first transistors and second interconnects essentially composed of metal are arranged perpendicular to the first interconnects. The second interconnects extend either over the transistors or between the transistors. Transistors respectively arranged in one of two groups are combined to form a parallel or series circuit. Metal tracks are arranged in the basic cell outside of the transistor surfaces at the lateral cell edge. Polysilicon interconnects and/or metal interconnects are established perpendicular to the appertaining directions, namely parallel to the extent of the transistors or, respectively, perpendicular thereto. The interconnects are arranged such that a respective following interconnect has its course adapted to the contour of the previously defined interconnects. Further, required contacts at the interconnects are arranged shifted with respect to the interconnects connected thereto such that they are dislocated into a bay contained at the appertaining, neighboring interconnect.