Arrangement and method for speeding the operation of branch instructions

摘要

Arrangement and method for avoiding the processing time associated with executing branch instructions in a computer. An instruction fetch unit appends a next instruction address field to each instruction it passes it via an instruction cache to an instruction execution unit. The fetch unit decodes the present instruction being read and the next sequential instruction in main memory. If neither instruction is a branch instruction, the next address field is set to the address of the next sequential instruction. If the present instruction is a branch, the next instruction address field is set to the branch address contained in the present instruction. If neither of these cases are true and the next sequential instruction from main memory is a branch, the next instruction address field is set to the branch address of this instruction. The execution unit uses the next instruction address to access instructions from the instruction cache. Thus, execution of branch instructions by the execution unit are avoided.