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Parallel binary adder having grouped stages including dynamic logic to increase carry propagation speed
Parallel binary adder having grouped stages including dynamic logic to increase carry propagation speed
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机译:具有分组级的并行二进制加法器,包括动态逻辑以提高进位传播速度
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摘要
A binary adder circuit is described using dynamic transistor logic in which for high speed carry propagation the adder stages are grouped in pairs or larger numbers and additional dynamic logic means is provided in each group to control a single transistor connected in series in the carry propagation path over the group. The transistors used in the specific embodiments are MOS transistors, but some or all of these could be replaced by junction FET's or bipolar transistors.
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