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INSTRUCTION BUFFER REPLACEMENT ALGORITHM

机译:指令缓冲区替换算法

摘要

PURPOSE:To improve a bit rate in an instruction buffer by providing a replacing direction bit and inverting the replacing order indicated by the replacing information bit of an instruction block by means of an output in a replacing direction. CONSTITUTION:A replacing direction bit 3 is provided and the replacing direction information of the bit 3 is sent to a replacing order preparing means 2 through a replacing direction information line 301. At the means 2 the exclusive OR of the output of a replacing information bit 21 and each bit is taken from the replacing order information by means of exclusive OR (XOR) gates 23 and 24. By leading output signals of the XOR gates 23 and 24 to T/C gates 25 and 26 and AND gates 27-30, replacing instruction blocks are decided and the replacement of instruction blocks is designated to respective instruction blocks 11-14 through instruction block replacement designating lines 201-204. Therefore, the bit rate of an instruction buffer is improved and the instruction execution processing speed can be improved.
机译:目的:通过提供替换方向位并通过在替换方向上的输出来反转指令块的替换信息位指示的替换顺序,来提高指令缓冲区中的比特率。组成:提供了替换方向位3,并且通过替换方向信息线301将位3的替换方向信息发送到替换顺序准备装置2。在装置2处,替换信息位的输出的异或在图21中,通过异或(XOR)门23和24从替换顺序信息中获取每个比特。通过将XOR门23和24的输出信号引导到T / C门25和26以及与门27-30,确定替换指令块,并通过指令块替换指定线201-204将指令块的替换指定给各个指令块11-14。因此,提高了指令缓冲器的比特率并且可以提高指令执行处理速度。

著录项

  • 公开/公告号JPH02103633A

    专利类型

  • 公开/公告日1990-04-16

    原文格式PDF

  • 申请/专利权人 NEC CORP;KOUFU NIPPON DENKI KK;

    申请/专利号JP19880256698

  • 发明设计人 KOBAYASHI NAOKI;KAMIYA YASUAKI;

    申请日1988-10-12

  • 分类号G06F12/12;G06F9/38;

  • 国家 JP

  • 入库时间 2022-08-22 06:26:22

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