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MULTIPLE INTEGRATION TYPE A/D CONVERTER

机译:多重积分型A / D转换器

摘要

PURPOSE:To simplify a circuit deciding the end of each integration cycle by changing the integration direction alternately in plural integration cycles and calculating digital ration through addition and subtraction corresponding to the charge or discharge for the count of the integration time, thereby allowing the end of each integration cycle to be decided through the comparison between the result of integration and a common prescribed value. CONSTITUTION:An integration circuit 1 stores a charge corresponding to an analog input signal Vin and applies integration in two integration cycles composed of the discharge and the charging of the charge. A charge/discharge circuit 2 has two current sources with a different current direction from the current to switch the discharging/ charging corresponding to the switching of the integration cycle. A comparator 3 compares the integration output of the integration circuit 1 with a prescribed value V1 to vary the output polarity. A control circuit 4 controls the switching of the integration cycle and the end of A/D conversion to each section. A counting circuit 5 adds or subtracts the clock signal CK based on an instruction issued from the control circuit 4 corresponding to the output polarity from the comparator circuit 3 synchronously with the switching command of the integration cycle to digitize the analog input signal Vin.
机译:目的:通过在多个积分周期中交替改变积分方向并通过对积分时间的计数对应于充电或放电的加减运算来简化数字来决定每个积分周期的结束,从而允许结束每个积分周期将通过积分结果与共同的规定值之间的比较来决定。组成:积分电路1存储与模拟输入信号Vin对应的电荷,并在两个由电荷的放电和充电组成的积分周期中进行积分。充电/放电电路2具有两个电流源,其电流方向与电流不同,以对应于积分周期的切换来切换放电/充电。比较器3将积分电路1的积分输出与规定值V1进行比较以改变输出极性。控制电路4控制积分周期的切换以及到每个部分的A / D转换的结束。计数电路5与积分周期的切换指令同步地基于与来自比较器电路3的输出极性相对应的,从控制电路4发出的指令,对时钟信号CK进行加法或减法,从而将模拟输入信号Vin数字化。

著录项

  • 公开/公告号JPH02254823A

    专利类型

  • 公开/公告日1990-10-15

    原文格式PDF

  • 申请/专利权人 SONY CORP;

    申请/专利号JP19890076906

  • 发明设计人 SASAKI TADAO;

    申请日1989-03-29

  • 分类号H03M1/52;

  • 国家 JP

  • 入库时间 2022-08-22 06:26:17

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