COMMON BUS ARBITRATING METHOD FOR MICROCOMPUTER SYSTEM

摘要

PURPOSE:To remove a waiting cycle which is unnecessarily inserted and to execute the transmission/reception of data with a small cycle by directly using a chip selecting signal obtained by decoding a common area address signal as a waiting releasing signal regardless of a common area write / read signal. CONSTITUTION:By using an address signal AD, a common area address signal CAD outputted from an address latch 104 of a bus master module to a common bus is decoded through an address decoder 31 on the side of common resource and a chip selecting signal, the inverse of CS is obtained to select the common resource. When this common bus is continuously used, the chip selecting signal, the inverse of CS is used as an waiting releasing signal, the inverse of Ready and a waiting signal RDY is immediately canceled through a NAND gate 107. When the using right of the common bus is newly obtained, the signal is delayed through a delay circuit 108 and given to the NAND gate 107. Accordingly, prescribed delay is executed to the waiting releasing cancel signal, the inverse of Ready and the waiting signal RDY is canceled. Thus, since the unnecessary waiting cycle is not inserted, the efficiency of data transfer can be improved.