MULTIPLEX DATA DEMULTIPLEXING AND FORMAT CONVERSION SYSTEM

摘要

PURPOSE:To reduce the mount area and cost in comparison with multiplex data demultiplexing and format conversion using plural ES by using a logic element as circuit constitution, using one elastic storage memory (ES) so as to apply demultiplexing format conversion of a multiplex data. CONSTITUTION:Only a data part of a multiplex data inputted from an input terminal 18 is written in an ES11 based on a write clock from a control pulse generating section PG17. Moreover, a multiplex data (data part) is read sequentially based on a readout clock independently of a write clock from the PG17 to the ES11. Delay circuits 12, 13 based on a delay clock from the PG17 retard the ES output data (a) by 2-bit and 1-bit and sends the result. The output and ES output data (a) of the delay circuits 12, 13 are given to D flip-flops 14-16 respectively. Then the D flip-flops 14-16 are operated by an output clock having a speed of 1/3 of the speed of the readout clock from the PG17.