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4-PHASE CLOCK GENERATING CIRCUIT FOR SWITCHED CAPACITOR FILTER

机译:开关电容滤波器的四相时钟产生电路

摘要

PURPOSE:To set a delay time to a desired time by providing a prescribed number of delay units as a delay, circuit for a 4-phase generating circuit for a switched capacitor filter and turning on required number of delay units at the adjustment at manufacture. CONSTITUTION:A delay circuit is provided in a 4-phase generating circuit for a switched capacitor filter(SCF). In the case of adjusting the delay of the 4-phase generating circuit, an output of a predetermined standard pattern is inputted in parallel with each pin of a register 251 of a setting circuit 25, for example, and the delay time at that time is measured, then whether the time is too long or too short is detected, and other pattern is selected, then an optimum delay is detected. When a control signal with a detected optimum delay is generated in an LSI, the circuit is operated afterward at the optimum delay time.
机译:目的:通过提供规定数量的延迟单元作为延迟,将延迟时间设置为所需时间,用于开关电容器滤波器的四相生成电路的电路,并在制造时进行调整时开启所需数量的延迟单元。构成:在4相产生电路中提供了一个延迟电路,用于开关电容滤波器(SCF)。在调整4相生成电路的延迟的情况下,例如,与设定电路25的寄存器251的各引脚并行地输入预定的标准模式的输出,此时的延迟时间为测量时,则检测时间是否太长或太短,并选择其他样式,然后检测最佳延迟。当在LSI中生成具有检测到的最佳延迟的控制信号时,此后电路将以最佳延迟时间工作。

著录项

  • 公开/公告号JPH02199918A

    专利类型

  • 公开/公告日1990-08-08

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP19890019192

  • 发明设计人 UJIIE HIROYUKI;

    申请日1989-01-27

  • 分类号H03K5/13;H03K5/133;H03K5/15;H03K5/151;

  • 国家 JP

  • 入库时间 2022-08-22 06:24:16

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