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4-PHASE CLOCK GENERATING CIRCUIT FOR SWITCHED CAPACITOR FILTER
4-PHASE CLOCK GENERATING CIRCUIT FOR SWITCHED CAPACITOR FILTER
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机译:开关电容滤波器的四相时钟产生电路
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摘要
PURPOSE:To set a delay time to a desired time by providing a prescribed number of delay units as a delay, circuit for a 4-phase generating circuit for a switched capacitor filter and turning on required number of delay units at the adjustment at manufacture. CONSTITUTION:A delay circuit is provided in a 4-phase generating circuit for a switched capacitor filter(SCF). In the case of adjusting the delay of the 4-phase generating circuit, an output of a predetermined standard pattern is inputted in parallel with each pin of a register 251 of a setting circuit 25, for example, and the delay time at that time is measured, then whether the time is too long or too short is detected, and other pattern is selected, then an optimum delay is detected. When a control signal with a detected optimum delay is generated in an LSI, the circuit is operated afterward at the optimum delay time.
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