FEEDBACK SHIFT REGISTER TYPE TEST PATTERN GENERATOR

摘要

PURPOSE:To obtain a high trouble detection rate when an integrated circuit is tested by providing an FF and a multiplexer which selects the output or inversion output of the FF to a register of each register which constitute a shift register. CONSTITUTION:When a control signal C1 is 0, respective multiplexers 105-108 select and output outputs Q which are inputted from FFs 101-104. In this case, when data of two optional successive FFs at certain time (t) are '00', possible data at time t+1 are '00' and '10'. Then when the signal C1 is 1 and the inversion output Q' is selected, possible data at the time t+1 are '11' and '01'. Two modes are used each once successively to obtain four kinds of possible data at the time t+1. Consequently, a high trouble detection rate can be obtained as to a circuit composed of a CMOS circuit.