PURPOSE:To improve a processing speed by reading an operand corresponding to the next address value to a temporary storage circuit simultaneously when an instruction is read from a storage device. CONSTITUTION:An instruction word and the operand of the instruction in a processor 1 are stored in a storage device 2 so that the address value of the storage device 2 can be continued. When a state generation part 11 of a processing circuit 1 sends an instruction fetch signal, the instruction word corresponding to address information is read out of the storage device 2 and stored to an instruction latch 14 of the processor 1. Simultaneously, operand information corresponding to the next address are read out and stored in a register in the storage device 2. Next, when the state generation part 11 generates an operand fetch signal, operand information already stored to the register are read out and stored in a operand latch 16 of the processor 1. Thus, an operand fetch time can be simultaneously shortened together with an instruction decode time and the processing time can be improved.
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