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MICRODATA COMPUTERS WITH QUICK STORAGE SYSTEMS WHICH CAN OPERATE IN A WORK WITH CONCERNING DIFFERENT STEPS IN AN OPERATION
MICRODATA COMPUTERS WITH QUICK STORAGE SYSTEMS WHICH CAN OPERATE IN A WORK WITH CONCERNING DIFFERENT STEPS IN AN OPERATION
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机译:具有快速存储系统的微数据计算机,可以在操作中以不同的步骤进行操作
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摘要
In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.
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