HARDWARE IMPLEMENTED CACHE COHERENCY PROTOCOLE WITH DUPLICATED DISTRIBUTED DIRECTORIES FOR HIGH-PERFORMANCE MULTIPROCESSORS

摘要

This disclosure describes a snooping coherency protocol for a multiprocessor network wherein every processor has its own private cache and bus interface means and the network is connected via a common system bus. Each processor has its own cache directory and image directory that duplicate each other non-atomically. The snooping protocol utilizes the duality of directories coupled with the non-atomicity of directory updates to maximize processor-cache availability and minimize processor-cache access times thus supporting high performance architectures.