Circuit arrangement for limiting, regulating and in some cases interrupting the collector current of the switching-transistor in the primary circuit of a switching power supply

摘要

1. Circuit arrangement for limiting, regulating and in some cases interrupting the collector current (Ic ) of the switching transistor (T) in the primary circuit, using a current probe (SF) connected in series to the switching transistor (T) and a control component containing a first comparator (V1) and a pulse-duration modulator (PDM), which control component influences the duty ratio of the switching transistor (T) as a function of a comparison value gained from the output signal of the current probe (SF) and a reference signal (UREF1 ), characterized in that the output of the current probe (SF) is connected to the first input of a second comparator (V2), the second input of which is fed with a reference signal (UREF2 ) which is higher in relation to the reference signal (UREF2 ) which is higher in relation to the reference signal (UREF1 ) of the control component (RBS), in that the output of the second comparator (V2) is connected to the set input (S) of a bistable flip flop (KS) and in that the output of the bistabile flip flop (KS) is fed to the input of a switch-off device connected upstream of the pulse-duration modulator (PDM).