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Apparatus and method for improving cache access throughput in pipelined processors
Apparatus and method for improving cache access throughput in pipelined processors
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机译:用于提高流水线处理器中的高速缓存访问吞吐量的设备和方法
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摘要
An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.
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