Parallel pseudorandom pattern generator with varying phase shift and method for simulating such a generator

摘要

Phase enhancement means are employed in conjunction with linear feedback shift registers to generate sequences of binary pattern vectors which are much more structurally independent of one another thus enabling more thorough and comprehensive testing of integrated circuit systems. More particularly, the present invention employs a plurality of exclusive-OR gates in an array of one gate per shift register output cell to generate the desired uncorrelated pattern strings. This facilitates testing of integrated circuit devices and systems and is particularly useful for built-in test situations for very large scale integrated circuits which employ pseudorandom test methods.