modular hochgeschwindigkeitsmultiplizierer, and integrated schaltungs modules for such multiplizierer.

摘要

In a high-speed multiplier the array of partial products is generated and reduced by means of similar integrated circuit chips of a first type each handling a square section (714, 716, 718, 720, 722, 724) of the array. …??The chip contains thirty-six AND gates, each receiving one digit of the multiplier and one digit of the multiplicand for its inputs, and whose outputs are fed to the first rank of a tree of pseudoadders, each of which is arranged to sum three input numbers and produce sum and carry outputs. The partial products produced by these chips are fed to a further rank of chips of a second type which further reduce the partial products to two in number, and these are finally combined by a full adder to produce the full product. …??Each chip contains means for generating the parity of its internal carries, thereby allowing the parity of the sums and carries produced by the array of chips to be generated and used for parity checking.