Memory system for image processing having address calculating circuitry permitting simultaneous access to block horizontal sequence and vertical sequence subarrays of an array of data

摘要

A memory system for storing an MN array of data elements and for permitting simultaneous access to selected block, horizontal sequence and vertical sequence subarrays defined by the parameters p and q comprises only (pg+1) memory modules for storing the MN array of data; address calculating apparatus which does not use any modulo-(pg+1) operations for determining the distribution of the data elements of a selected subarray among the memory modules and for alocating different addresses to subarray data elements assigned to the same memory module according to memory module assignment and address assignment functions; address routing apparatus separate from the address calculating apparatus for routing the addresses produced by the address calculating apparatus to the memory modules; data routing apparatus for routing the data elements to the memory modules; and control and enabling apparatus for controlling the address calculating, address routing and data routing apparatus and for enabling only pg of the (pg+1) memory modules for storage of the data elements of the selected subarray, only one modulo- (pg+1) operation being required for the address routing and memory module enabling functions.