Serial communications controller with FIFO register for storing supplemental data and counter for counting number of words within each transferred frame

摘要

A single chip serial communications controller, adapted for transfer of data to memory in a direct memory access interrupt, generates a status word for each frame of data. To allow for uninterrupted transfer of data to memory from frame to frame, the status words are stored in a FIFO along with word counts corresponding to the frames to allow for subsequent identification of the addresses to which the data frames are assigned. The FIFO is incremented at the end of each frame and decremented as each status word is read by a CPU.