Frame synchronization device for a synchronous digital bit stream divided into blocks by means of a block code and structured in frames

摘要

A frame synchronization device for a synchronous digital bit stream divided into blocks by means of a block code and structured in frames comprises a frame alignment word configuration recognition circuit generating for each recognized configuration a recognition signal that is directed to a frame alignment acquisition control circuit through the intermediary of a configuration selection circuit. This circuit operates under the control of a time window definition circuit driven by a block timebase and a frame timebase and is adapted to select only recognition signals corresponding to alignment word configurations correctly placed relative to the blocks. The sorting done by the configuration selector eliminates most imitation alignment words and therefore accelerates significantly the synchronization process.