PIPELINE TYPE ERROR INSPECTION/CORRECTION CASH MEMORY AND CASH MEMORY ARRAY

摘要

PURPOSE: To obtain an error inspection and correcting function for a cache memory without increasing a time by inserting a cycle by the control circuit of a cache chip and a CPU chip when a single error is detected. CONSTITUTION: An output from a cache array 12 is supplied to a hamming ECC 2-40 in the second cycle of an FETCH operation, and an error flag for a single error and corrected data are generated. Only at the time of the signal error. a third cycle is inserted by the control circuit of the cache, results from the hamming ECC 2-40 are latched by pipe line registers R2-42 in the beginning, and selected by a multiplexer 45, and transmitted to a CPU. Also. the corrected data in the register R2-42 are written and returned through a merge circuit 44 and a hamming circuit 46 to the array 12, and the storage of an error is prevented. When the multiplexer 45 is used in an additional cycle. the delay of the circuit ECC 2-40 can be removed and a bypass for reducing the cycle time can be formed from the path of the FETCH operation.