DOUBLE PRECISION ARITHMETIC SYSTEM AND ARITHMETIC UNIT FOR SUM OF PRODUCTS

摘要

PURPOSE:To decrease the number of arithmetic cycles by adding partial products whose digits are matched, each other in one arithmetic cyle while executing shift processing to the partial product. CONSTITUTION:Data read from data buses 4 and 5 can be parallelly supplied to a multiplier 6 and an arithmetic theory computing element 7 and the arithmetic result of the multiplier 6 is held in a buffer register 8 for one instruction cycle period and applied to the computing element 7. The computing element 7 executes addition and subtraction, etc., to the data, which are selectively applied from the register 8 or a data bus 3 through a selector 15, and a result is once held in accumulators 9A and 9B and returned to the bus 3 afterwards. When a carry is generated in the addition processing of the computing element 7 and the state is held in carry flags 16A and 16B and transmitted at prescribed timing as the carry signal of the prescribed input bit of the computing element 7. Thus, the number of the arithmetic cycles can be reduced.