PROGRAMMABLE LOGIC CONTROLLER SYSTEM TO CONTROL A NETWORK FOR MACHINE AND PROGRAMMABLE LOGIC CONTROLLER

摘要

A multiple processor communications system including a control processor and a scan processor having its own program counter enabling the efficient execution of subroutines. The scan processor directly accesses a compiled user memory which contains its operating program and also directly accesses the image memory which contains the input and output data to perform the computations required by the program. The system includes error codes for distinguishing various error conditions including collision error conditions indicating illegal commands to the scan processor when it is scanning and parity errors in the compiled user memory and in the image memory.