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phasenregelschleife for filter array with non rationellem relationship between the a - and ausgangsabtastfrequenz.
phasenregelschleife for filter array with non rationellem relationship between the a - and ausgangsabtastfrequenz.
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机译:滤波器阵列的相位控制环路在a和输出采样频率之间具有非理性关系。
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摘要
In a sample rate converter having a non-rational conversion factor the input samples coincide with low-rate clock pulses and the output samples coincide with high-rate clock pulses, or inversely. It comprises a filter coefficient generator which, based on the distance (deviation) between a low-rate clock pulse and the immediately preceding or immediately subsequent high-rate clock pulse, continuously supplies a series of filter coefficients. To determine the deviation a phase-locked loop is provided, with a phase detector receiving the low-rate clock pulses as well as synthetic low-rate clock pulses and supplying a discrete-time phase difference signal which is applied to a processor circuit. This circuit supplies the desired deviation and a reference number which is applied to a counter circuit. This circuit also receives the high-rate clock pulses and each time after receiving the number of clock pulses corresponding to the reference number it supplies a synthetic low-rate clock pulse. In the processor circuit a filtering operation is first performed on the discrete-time phase difference signal so that control signal samples are obtained. An auxiliary sample is subtracted from such a control signal sample and the difference is divided by a weighting factor of the number P thus obtained those bits whose significance is less than 2 DEG represent the deviation, while the other bits represent the reference number. By subsequently multiplying the deviation by the weighting factor, a new auxiliary sample is obtained.
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