FRAME CHECKING ARRANGEMENT FOR DUPLEX TIME MULTIPLEXED REFRAMING CIRCUITRY

摘要

A FRAME CHECKING ARRANGEMENT FOR DUPLEXTIME MULTIPLEXED REFRAMING CIRCUITRYABSTRACT OF OF INVENTIONTelecommunication switching systems are typicallyconnected by high-speed digital data spans. These spans maycommonly be T1 or T2 carriers using DS1 or DS2 data formats,respectively. These systems may contain duplex digital spancontrol units. Synchronization circuitry includes a timemultiplexed state machine for each copy of the digital spancontrol unit. The state machine monitors framing alarm signalsfrom its own copy as well as from the other copy of the digitalspan control unit. This circuitry detects whether the framingalarm signals for each copy are identically synchronized. Ifthese framing alarm signals are not identically synchronized, thenone copy of the circuitry executes a hold (wait) operation for theother copy of the circuit to perform its reframing operation. Fornon-error conditions, the wait places the two copies back insynchronization. This arrangement applies stringent checkingcriteria to framing and synchronization bits, which have beenpreviously found, to insure that these bits are the correct ones.As a result, the duplex units are more likely to remainsynchronized.