PROCESSOR ARRAY COMPRISING PROCESSORS CONNECTED SELECTIVELY IN SERIES OR IN PARALLEL

摘要

Abstract of the DisclosureIn a processor array comprising first throughN-th processors, each of first through (N-1)-thswitching devices is connected between preceding andsucceeding processors of two consecutively numbered onesof the first through the N-th processors. Eachprocessor comprises at least one processor modulebetween a processor input bus and a processor outputbus. A controlling unit controls the first through the(N-1)-th switching devices so that the processor inputand output buses of the first through the N-thprocessors are selectively connected together. Eachprocessor may further comprise a feedback bus connectedto the at least one module. In this case, the firstthrough the (N-1)-th switching devices are controlled sothat the feedback buses of the first through the N-thprocessors are selectively connected in series incompliance with the manner in which the processor inputand output buses of the first through the N-thprocessors are connected together. When each processorcomprises a plurality of processor modules, thecontrolling unit may furthermore control the processormodules of each processor so that the processor modulesof each processor are selectively operable. Theprocessor modules of one or more processors may processpartial blocks of each principal block of a digitalvideo signal, respectively, during a time duration ofthe principal block. The control unit may put theprocessor modules into operation either only once ineach time duration or repeatedly in a time divisionfashion.