Apparatus for the optimization of the performances of real-time primitives of a real-time executive kernel on multiprocessor architectures

摘要

The device comprises a real-time operator OTR formed by a microprogrammed circuit connected to the BUS memory (Bc) which is common to the processors of the multiprocessor structure. As seen by a processor, this operator OTR behaves like a common memory zone and possesses circuits for address recognition, for transmission and reception of the data to be processed and for generating signals for monitoring exchanges. It consists of at least two stand-alone units (A1, A2) which are dedicated respectively to the management of certain real-time objects. These stand-alone units intercommunicate via a BUS (BUS OTR) internal to the operator. The invention applies in particular to multimicroprocessor structures on board aircraft. IMAGE