A technique for generating an address during an instruction decode cycle in a RISC processor

摘要

Apparatus and accompanying methods, particularly suited for use in conjunction with pipelined instruction processing occurring in a processor of a reduced instruction set computer (RISC), for generating an address during a decode cycle of the instruction processing. Use of this technique substantially eliminates a wait state frequently caused by an address generation cycle that otherwise occurs during pipelined processing of RISC instructions and thereby advantageously increases the processing speed of the RISC processor. In particular, a RISC instruction is both fully decoded and pre-decoded in parallel. The pre-decoding is used to extract the displacement field from the instruction, select a proper base address for the current RISC instruction and, in conjunction with formatting operations, properly align the displacement field - all within the current decode cycle. The base and aligned displacement addresses are then applied to separate inputs of an address adder. The output of the adder is propagated through an address register to an output as a memory address during the decode cycle in the event the full instruction decoding confirms that the current RISC instruction does require an address to be calculated; otherwise, the calculated address produced by the adder during this decode cycle is merely discarded by being over-written during a decode cycle for a subsequent RISC instruction.