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Method for providing synchronized data cache operation for processors in a parallel processing system, and parallel processing system implementing the method

机译:为并行处理系统中的处理器提供同步数据缓存操作的方法以及实现该方法的并行处理系统

摘要

Apparatus and method for insuring data cache content integrity among parallel processors. Each processor has a data cache to store intermediate calculations. The data cache of each processor is synchronized with each other through the use of synchronization intervals. During entry of a synchronization interval, modified data variables contained in an individual cache are written back to a shared memory. The unmodified data contained in a data cache is flushed from memory. During exiting of a sychronization interval, data variables which were not modified since entry into the synchronization interval are also flushed. By retaining modified data cache values in the individual processors which computed the modified values, unnecessary access to shared memory is avoided.
机译:用于确保并行处理器之间的数据高速缓存内容完整性的设备和方法。每个处理器都有一个数据高速缓存,用于存储中间计算。每个处理器的数据高速缓存通过使用同步间隔彼此同步。在输入同步间隔期间,单个高速缓存中包含的已修改数据变量将写回到共享内存中。数据高速缓存中包含的未修改数据将从内存中清除。在退出同步间隔期间,还将清除自进入同步间隔以来未修改的数据变量。通过将修改后的数据缓存值保留在计算修改后值的各个处理器中,可以避免对共享内存的不必要访问。

著录项

  • 公开/公告号EP0453028A2

    专利类型

  • 公开/公告日1991-10-23

    原文格式PDF

  • 申请/专利权人 PHILIPS ELECTRONICS N.V.;

    申请/专利号EP19910200858

  • 发明设计人 WHELAN MICHAEL;

    申请日1991-04-12

  • 分类号G06F12/08;

  • 国家 EP

  • 入库时间 2022-08-22 05:52:25

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