BUS ARBITRATION CIRCUIT IN ROUND-ROBIN SELECTING METHOD

摘要

A bus arbitration circuit features incorporating bus masters with same priorities for VME bus system, while there was performance degradation caused by bus grant delayed up to 4-olock period upon bus request signal. Thus it minimizes bus arbitration time and its error. The system consists of multiplexer (10) for bus request input, choosing output and interrupting other request, control signal generator (20) for the first and second control signal, counter (30) for data count, decoder (40) to decode counter output and to give selecting signal, the first-fourth bus arbiter (50-80) and gates (91-94) to generate corresponding bus grant signal to request signal by logic combination.